Calculator system featuring relative program memory

ABSTRACT

Disclosed is a portable hand-held calculator system implemented in semiconductor LSI technology which features relative instruction memory addressing. A permanent store instruction memory is provided for storing a relatively large number of instruction words at specific addresses with each instruction word providing either a branch or an instrction command. The instruction word is a multi-bit word which, if one bit therein commands a conditional branch, has a set of digits representing a relative address number which either positively or negatively increments the old address to provide the address next in sequence. Another bit of the instruction word is a condition bit utilized in a compare with a representation of an internal operating condition of the calculator system. If a proper match is realized, a conditional branch is executed. A full adder selectively increments the previous instruction word in response to the relative address to generate the new instruction word.

United States Patent Cochran et al.

[ 1 Nov. 25, 1975 CALCULATOR SYSTEM FEATURING Primary Examiner-David H,Malzahn RELATIVE PROGRAM MEMORY Attorney, Agent, or Firm-Harold Levine;Rene E. [75] Inventors: Michael J. Cochran, Richardson; Grossman; ThomasDevme Charles P. Grant, Jr., Dallas, both of 57 ABSTRACT [73] Asslgnee:B hjrstrumems Incorporated Disclosed is a portable hand-held calculatorsystem a implemented in semiconductor LSl technology which [22] Filed:Sept, 13, 1973 features relative instruction memory addressing, A Ipermanent store instruction memory is provided for [2H Appl 396302storing a relatively large number of instruction words at specificaddresses with each instruction word pro [52] U5. Cl 235/156; 340/172.5i ing ith r a ranch r an in rc i n ommand The [51] Int. Cl. G065 9/20instruction word is a multi-bit word which, if one bit [58] Field ofSearch 235/156; 340/172.5 therein commands a conditional branch, has aset of digits representing a relative address number which [56] Referenes Cited either positively or negatively increments the old ad- UNITEDSTATES PATENTS dress to provide the address next in sequence, An-3,4os,s30 10/1968 Packard et al 340/1725 q p of the msmicmn word F l3'570006 3/1971 Hoff at al n 340N725 lized in a compare with arepresentation of an internal 3577.139 5l97] Cocke e a] H 340/1725operating condition of the calculator system. If :1 3,614,747 1971[Shihara e 340/1725 proper match is realized, a conditional branch isexe- 3,705.389 12/1972 Krock et al, 340/1725 cuted. A full adderselectively increments the previous 3,728,686 4/1973 Weisbecker 340/1725instruction word in response to the relative address to 3,728,689 4/l973Edwards, Jr. 340/1725 generate the new instruction word, 3,748,4517/1973 lngwersen 235/156 10 Claims, 79 Drawing Figures 1 2 & RBQszLEcT Ea d I CONSTANT a S P m u REGXSTER E S p m ADDRESS I 1 1 HQ 0) l! v U o Em o N i i s P ROM E I? I4 1 g gi *5 15 m U s p ADDER l! 32 f? cs a QRECALL 8 El CONSTANT O t O U 3 E m Q 85 3. a 52 :2 23 U 35 z u 1 s z 551 ADDRESS l- DECODER fi; g I I CONSTiA- D1 8 U0 5/ r 37 :0 27 CONTROL IBUFFER 1; 12. 1/0 i/o [i] lRG U.S. Patent Nov.25, 1975 Sheet10f633,922,538

U.S. Patent Nov. 25, 1975 Sheet 2 of 63 3,922,538

PROGRAMMER CHIP Fig. 2

MEMORY STORAGE PRINTER CHIP BUSY

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US. Patent Nv.25, 1975 Sheet6of 63 3,922,538

Fig. b

I M0 Flag Operation I Brannaof 11 Ml All Mask ll COndltlOn:I (md) M2 DPTMSR M3 DPT 1 M A DPT c I M5 LLSD 1 10 (me) M6 EXP MSB M7 EXP 1 M8KEYBOARD OPERATIONS I M9 MANT 9 (mb) M1O wAIT OPERATIONS M11 MLSD 5 M12MAEX LSB I M13 MLSD 1 8 (ma) Mlu MMSD 1 J M MAEX 1 I R0 A N 7' R1 B+N(Rd) R2 c N MSB R3 O+N I6 Ru Shift A Relative R5 Shift B Branch (RC) R6Shift C I Address R7 Shift D 5 7 R8 A+B Fig 5a 15 R I I R10 CiD R11 AiBI I R12 AiConstant A R13 NO-OP (Ra) Rl l 0+ Constant I LSB J R15RE-Adder (Mask LSD) I =O:add=shift left I2 (Sub) =l:sub=shift right LSBMSB YO=Z-A J Tl=Output I/O I O IN j I EQIA-R 0 g%$% l 5, 3TB (EFFECTIVEFOR 1 (Yb) H: THC WHOLE INSTRUC- gg g-g TION cYcLE WITH 1 ANY DIGIT MASKIO ?7:AE

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US. Patent N0v.25, 1975 Sheet70f63 3,922,538

The following 8 bits effective only if flag operationS 7 (fmd) MSB I6 IThe following 8 bits effective Generate FlagMaSK only if Keyboardoperations when these '4 bits equal the "4 encoded State I bitS =O=SCANKYBD (NOTE: ENCODED STATE TIMES ARE +2 FROM ACTUAL STATES) i 7 =1=KT(fma) LSB 5 =O:KS

The following U- bitS (flagopS) effective only during flagmasK I w u 515 5 =O=KR O TEST FLAG A A Q 1 TEST FLAG B a 2 SET FLAG A I I2 3 SETFLAG B 2 ZO=KP (fd) a ZERO FLAG A I MSB 5 ZERO FLAG B 11 1 6 INVERT FLAGA C INVERT FLAG B IO 8 EXCH. FLAG A B =O=KN (fb) 9 COMPARE FLAG A B lOSET FLAG KR ll ZERO FLAG KR F/g, LSB l2 COPY FLAG B-A 13 COPY FLAG A-B ll REG 5-FLAG A S0 S3 15 REG 5*FLAG B S0 S3 Fig 5c US. Patent Nov. 25,1975 Sheet9of63 3,922,538

2 P 2 2 l| DH P S Uli: PE 2 M n a l T .0 L S 0' US. Patent ARITHMETICCHIP Nov. 25, 1975 Sheet 11 of 63 3,922,538

TO DISPLAY A x KN 5 4 3 z 1 K0 ,1 m KP 53 Y 6 L0 x! EL I KR l s j-9 1 KTii w r-1 1.]

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US. Patent Fig, 80

Nov. 25, 1975 Sheet 12 0f 63 Fig. 8bl

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US. Patent Nov. 25, 1975 Sheet 13 0f 63 3,922,538

fMSK' VDD US. Patent Nov. 25, 1975 Sheet 14 0f63 3,922,538

Fig. 862

US. Patent Nov. 25, 1975 Sheet 15 0f 63 3,922,538

U.S. Patent Nov. 25, 1975 Sheet 16 of63 3,922,538

Fig, 80 4 0mm c 52: OM5 60 ANYDMD 0/5 sra Sl-UFI D U.S. Patent Nov. 25,1975 Sheet 17 of 63 3,922,538

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o/v new U.S. Patent Nov. 25, 1975 Sheet 18 0f 63 3,922,538

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Pawn? UP Mrcf/ (mar 3) Von US. Patent Nov. 25, 1975 Sheet 19 0f 633,922,538

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1. A portable electronic calculator system having keyboard entry meansand a system clock for providing timing cycles, comprising: a. permanentstore instruction memory means for storing a plurality of instructions;b. addressing means for addressing a particular location in the memoryto procure an instruction word, and for storing the current address; c.control word generating means for providing a multi-bit control word; d.comparison means, for comparing a specified portion of the instructionword with a specified portion of the control word; and e. addressmodifying means operatively connected to the addressing means andresponsive to one condition of the comparison means for adding orsubtracting a predetermined number to or from, respectively, the currentaddress, the address modifying means including incrementing means,responsive to another condition of the comparison means, forincrementing the current address by a fixed increment.
 2. The system ofclaim 1 wherein the control word generating means further compriseregister means operatively connected to receive multi-bit words from thekeyboard entry means, and having output means connected to thecomparison means.
 3. The system of claim 2 wherein the address modifyingmeans comprise a full adder, responsive to the cmparison means foradding or subtracting a selected portion of the instruction word to orfrom, respectively, the current address.
 4. The system of claim 3wherein the comparison means further comprise: d. i. a comparator forcomparing the specified portion of the instruction word with thespecified portion of the control word; and ii. branching means,responsive to the comparator, for transmitting the selected portion ofthe instruction word of the instruction word to the full adder.
 5. Thesystem of claim 4 wherein the incrementing means further comprise aunitary adder operatively connected to the comparator and responsivethereto for adding one to the current address in response to the othercondition from the comparator.
 6. The system of claim 2 wherein theoutput means of the register means is a serial output responsive to thetiming cycles.
 7. The system of claim 6 wherein the comparator isresponsive to the timing cycles to perform the comparison at a specifiedtime.
 8. The system of claim 7 wherein the instruction memory meanscomprise a semiconductor read-only-memory.
 9. In a portable electroniccalculator system having keyboard entry means, a system clock forproviding timing cycles and an instruction memory for storing andselectively providing an instruction word and having an address registerfor addressing the memory and for storing the current address, a methodof addressing the memory comprising the steps of: a. generating acontrol word in response to an entry from the keyboard entry means; b.comparing a specified portion of the control word with a specifiedportion of the instruction word located at the current address; c.adding or subtracting a predetermined portion of the instruction word toor from, respectively, the current address in response to one conditionof the comparing step and; d. incrementing the current address by afixed increment in response to another condition of the comparing step.10. The method of claim 9 further including, before the step ofcomparing, the steps of: d. serially transmitting the control word; ande. synchronizing a predetermined bit of the control word and apredetermined bit of the instruction word with the timing cycles toprovide a comparison at a specified time.